The present invention relates to a charge transfer device, particularly one for use as a CCD (charge coupled device) analog field memory.
An example of a conventional CCD analog field memory is shown in the Transactions of the Institute of Electronics and Communication Engineers of Japan, ED84-76 (1984), pp. 47-62, and will be described with reference to FIG. 2.
As illustrated in FIG. 1, the analog field memory comprises an input circuit 1 sampling an analog signal, an input serial reister 2 havin a pluralitY of stages connected to the input circuit 1, a parallel reister 4 having a plurality of channels connected through transfer gates 3 to the input serial reister 2, an output serial register 6 having a plurality of stages connected through transfer gates 5 to the parallel register 4, and an output circuit 7 connected to the output serial register 6. The output circuit 7 converts the signal charges through the output serial register 6 into voltage signals or current signals and produces them as output signals. A device having such a structure is generally called an SPS (serial-parallel-serial) charge transfer device.
When an analog signal IN is sampled by the input circuit 1, a signal charge corresponding to the sample value of the analog signal is inputted to the first stage of the input serial register 2. The inputted charge is transferred through the input serial register 2 in accordance with clock pulses applied to the input serial register 2. When all the stages of the input serial register 2 are filled with the signal charges, the transfer gates 3 are opened in accordance with a clock pulse, and the signal charges are transferred to the parallel register 4. Such an operation is repeated, and the signal charges within the parallel register 4 are transferred, in accordance with clock pulses applied to the parallel register 4, toward the output serial register 6 (in the direction of arrow A in FIG. 1).
When the signal charges arrive at the final stages of the parallel register 4, the transfer gates 5 are opened in accordance with a clock pulse, and the signal charges in the final stages of the parallel register 4 are concurrently transferred to the output serial register 6. The signal charges in the output serial register 6 are successively outputted in time sequence through the output circuit 7 in accordance with clock pulses applied to the output serial register 6.
FIG. 2 shows waveforms of the signals which appear where the output signals from the output circuit 7 do not contain noises.
The device of the above described arrangement has the following problems.
(1) When signal charges are transferred through a silicon chip forming the charge transfer device, a leak current called a dark current may flow. lf such a dark current flows, noise charges occur because of the dark current, resulting in noise signals X which are superimposed, as is shown in FIG. 3, on the signal charges to be transferred. As a result, the output signals are distorted. Such an effect is greater as the ambient temperature of the silicon chip is increased.
(2) The signal degradation due to the dark current differs from one stage to another of the output serial register 6. Where the correction of the output signals is made outside, the output signals from the outut serial register 6 are digitized and then stored in a digital memory, and the stored values are converted into analog signals and the resultant values ar used to obtain differences for the respective stages of the output serial register, thus requiring complicated circuits.